1. Field of Invention
The present invention is related to calibration and testing of semiconductor chips and in particular to the self-trimming and self-testing of on-chip analog values.
2. Description of Related Art
Integrated circuits use a wide collection of analog circuitry to enable the function of the integrated circuits ranging from reference voltages to reference currents, offsets, comparator thresholds and oscillator frequencies. Imperfection in the manufacture of the chips containing the integrated circuits results in the need to trim the values produced by the analog circuitry to produce a chip that might not function properly as designed. When performing multi-site testing, for instance semiconductor chips on a wafer, trimming cannot be done in parallel because the ATE (automatic test equipment) must react to the individual behavior of circuits on the various chips, individually calculate trim values and then send these values to the individual circuits.
U.S. Pat. No. 7,352,230 B2 (An) is directed to an internal power voltage trimming circuit and a method for individually or simultaneously performing level trimming for a plurality of power voltages in a semiconductor memory device. U.S. Pat. No. 7,284,167 (Le et al.) is directed to a method for providing programmable test conditions used in a BIST for a flash memory device. In U.S. Pat. No. 6,943,616 B2 (Ogawa et al.) an integrated circuit device and method is directed to adjusting an analog signal output without outputting the analog signal outside the integrated circuit device. U.S. Pat. No. 6,909,642 B2 (Lehmann et al.) is directed to integrated circuit chips having self-adjusting internal voltages and the method thereof. In U.S. Pat. No. 6,504,394 B2 (Ohlhoff) a circuit is directed to a configuration for trimming reference voltages within integrated circuit chips. U.S. Pat. No. 6,433,714 (Clapp et al.) is directed to methods and apparatus for trimming semiconductor devices and circuits. In U.S. Pat. No. 6,114,920 (Moon et al.) an auto-trim is directed to trimming a PLL oscillator operating curve for use during normal operations, wherein a state machine applies a digital control to a VCO during the auto-trim that is to be used in normal operations. U.S. Pat. No. 6,111,471 (Bonneau et al.) is directed to an apparatus for setting the free-running frequency of a VCO to a reference frequency and comprises setting the VCO within a frequency range and between frequency ranges. In U.S. Pat. No. 5,550,512 (Fukahori) a method is directed to providing a DC offset trim for automatic gain control independent of temperature and gain using a trim current connected to an AGC circuit. U.S. Pat. No. 5,319,370 (Signore et al.) is directed to a method and apparatus for calibrating errors in an analog reference voltage input to an ADC using a delta-sigma A/D converter.
In FIG. 1A is shown a block diagram of prior art for trimming a circuit under trim (CUT) 11 on an integrated circuit chip 10. The purpose of trimming is to overcome chip process variations in order to provide a more accurate analog signal and improve chip yield. The trimming operation is performed using automatic test equipment (ATE) to deliver digital trim data to the chip and monitor the analog trim values created by a CUT, which results from the digital trim data. As shown in FIG. 1A, an ATE 12 connects digital trim data to core logic 13 on the integrated circuit chip 10 where it is stored in a register 14. The core logic 13 connects the digital trim data to the CUT 11, which produces an analog signal. The analog signal is connected back to the ATE through an analog multiplexer 14. The ATE measures the untrimmed value of the analog signal and calculates a digital trim value that is connected to the core logic 13. The trim value is connected to the CUT where the process can be iterative depending upon the measured results of the trimmed analog signal output of the CUT. Once a trimmed value has been determined, the trim value is stored in a nonvolatile memory on the integrated circuit chip 10. The trim operation is performed in series with further testing of the integrated circuit and consumes valuable test time.
FIG. 1B shows how the natural distribution of a trimmed output of the CUT might be not centered where the target trim value is off center in on direction or another depending upon the algorithm used in trimming the CUT. FIG. 1C shows an ideal block distribution where the target value is centered within a +½ and a −½ least significant bit (LSB).